A thyristor can be a solid-state semiconductor device with at least four layers of alternating n-type and p-type material. Generally, thyristors are utilized as electrical switches that turn on with the application of a threshold current or voltage. A typical thyristor can include three leads, which may be referred to as an anode, a cathode, and a gate, where the gate controls the current that flows between the anode and the cathode. A small trigger current applied at the gate can allow for a larger current to flow between the cathode and anode, thus allowing the thyristor to serve as a switch within an external circuit.
A thyristor can be forward blocking, reverse blocking, or forward conducting. In a forward blocking mode, the anode is positive biased, the cathode is negative biased, and no current is supplied to the gate, thus no current can flow from the anode to the cathode. If no current can flow from the anode to the cathode, the thyristor is switched off. In a reverse blocking mode, the anode is negative biased and cathode is positive biased, and thus no current can flow through the thyristor. In a forward conducting mode, the anode is positive biased, the cathode is negative biased, and current is supplied to the gate. In a forward conducting mode, the alternating n-type and p-type layers generate a conductive state via movement of electrons and holes until an emitter region is adequately charged to be turned-on (i.e., saturated). Once the emitter region, or at least a substantial portion of the emitter region, is turned-on, current can flow from the anode to the cathode. The charging of the layers occurs in a propagating manner such that the turned-on area “spreads” throughout the emitter region to transition the emitter region into a turned-on state. This is known as spreading of the turned-on area. A measure of the rate at which the turned-on area spreads can be the derivative current capability (the “current capability” or the “di/dt capability”) of the thyristor.
The di/dt capability of a thyristor generally decreases as the blocking voltage (i.e., the maximum voltage applied to the thyristor before turning on) increases. This inverse relationship between the di/dt capability and the blocking voltage can occur because of the low spreading rate of the initial turned-on area and an increase of power loss at the turned-on area, both of which occur as the voltage applied to the thyristor is increased. As the result, the di/dt capability of a conventional high voltage thyristor, e.g., a 6 kilo-Volt (“kV”) class thyristor, is approximately 100 Amps/microsecond (“A/μs”).
Within this disclosure, a thyristor (“Th”) may be referred to as a silicon-controlled rectifier (“SCR”). Some skilled in the art reserve the term SCR for a particular type of thyristor, while others use SCR synonymously with thyristor. Within this disclosure the terms thyristor and SCR are synonymous and can be interchanged.
As noted above, a thyristor can be a semiconductor device that may include four layers comprising alternating p-n-p-n type material, which are generally denoted as pE layer, nB layer, pB layer, and nE layer. FIG. 1A shows a top view of a conventional thyristor device; FIG. 1B shows a schematic diagram of the conventional thyristor of FIG. 1A; FIG. 1C shows a cross sectional view along the A-A line of the conventional thyristor of FIG. 1A; and FIG. 1D shows a cross sectional view along the B-B line of the conventional thyristor of FIG. 1A.
As shown in FIGS. 1C-1D, an original n-type semiconductor wafer (e.g., silicon wafer) can form an n-base layer (or nB layer) 1, where the pE layer 2 may be formed on one side of the nB layer 1 so as to form a lower surface 8 of the device and the p-base layer (or pB layer) 3 may be formed on an opposite side of the nB layer 1 so as to form an upper surface 7 of the device. The nE layer 4 can then be selectively formed on the pB layer 3 so that portions of the pB layer 3 remain exposed. Some of the exposed pB layer 3 portions may then be configured as short dots 5 (e.g., an exposed pB layer 3 covered with an oxide), and at least one other exposed pB layer 3 portion can be configured as a gate area 6. Generally, the short dots 5 are distributed within the nE layer 4, and the gate area 6 is surrounded by the nE layer 4, where the nE layer 4 surrounding the gate area 6 can be referred to as the auxiliary nE layer 4′. Note that FIGS. 1C-D are partial cross sections through a middle of the device, and thus the gate electrode 11 and gate area 6 are in the middle of the device.
The auxiliary nE layer 4′ may be electrically connected to the gate area 6 at the upper surface 7 by metal to form an auxiliary thyristor cathode electrode 14. The auxiliary thyristor cathode electrode 14 can be further connected to the gate area 6 so as to be formed around the auxiliary nE layer 4′, wherein the region of the device comprising the auxiliary thyristor cathode electrode 14, the gate area 6, and the auxiliary nE layer 4′ can be referred to as the auxiliary thyristor region 15. The short dots 5 are in ohmic contact with their respective exposed nE layer 4 by a cathode metal to form the main thyristor cathode electrode 9. The gate electrode 11 is formed by a metal making ohmic contact with the gate area 6, but without direct contact to the gate area's 6 respective nE layer 4. The resultant structure facilitates the forward and reverse blocking capabilities of the thyristor.
The short dots 5 can also be used to improve forward blocking voltage capability and time derivative voltage capability (“voltage capability” or “dv/dt capability”) of the thyristor. For example, short dots 5 can make a parallel bypass resistance path underneath the pB-nE junction (see FIG. 1C) so that hot leakage current and displacement current, due to the dv/dt, flow through the bypass resistance path to the main thyristor cathode electrode 9. If the short dots 5 are not between the pB-nE junction 19, excess holes would exist at the pB-nB junction 19 during a forward blocking mode of the thyristor. Consequently, the excess holes would pile up underneath the nE layer 4, generating excess charge and biasing the pB-nE junction 19 forward. As the result, the thyristor may lose forward blocking capability, whereby the thyristor would turn-on when lower voltages are applied, which is estimated from the resistivity of nB layer 1. Thus, use of short dots 5 can decrease the pile up of holes underneath of nE layer 4, resulting in an improvement to the forward blocking and dv/dt capability of the conventional thyristor.
When a threshold plus (or positive) gate signal is applied to the gate area 6, the thyristor transitions from voltage blocking mode to low resistance mode, whereby current begins to flow. This can be referred to as the turn-on mode. As explained above, when a region becomes adequately charged, that region saturates with charge and propagates throughout the layers to generate a turned-on area. Once enough of the main thyristor region 16 is turned-on, current can begin to flow from the anode electrode 10 to the cathode electrode 9. The beginning of current flow through the thyristor can be referred to as the initial turn-on stage. With conventional thyristors, the initial turned-on area is limited to an area that is periphery to the gate area 6, or the gate periphery 17. As a consequence, the initial turned-on area spreads gradually over time to the main thyristor cathode electrode 9 and to the cathode electrode 9 (e.g., approximately 0.1 millimeter per micro-second (“mm/μs”)).
The rate at which the turn-on area spreads depends on the time it takes to electrically charge and modulate the injected holes of the nB layer 1 by the electrons from the pE and nE layers 2, 4. The time required to charge the holes increases as the thickness of the nB layer 1 increases, and the thickness of the nB layer 1 increases as the blocking voltage increases. Therefore, the rate at which the turned-on area spreads decreases as blocking voltage increases. Furthermore, as the blocking voltage increases, the actual applied voltage required to operate the thyristor (i.e., the applied switching voltage) increases, which means that the voltage applied within the circuit connected to the thyristor also increased. As a consequence, there is an increase in current supplied to the thyristor during the initial turn-on stage, as well as an increase of instantaneous power loss of the product voltage. The instantaneous power loss is a function of both instantaneous voltage v(t) and instantaneous current i(t), and the current i(t) depends on the rate of rise of on-state current (di/dt). From these relationships and the structure of the prior art device, one can appreciate that a combination of a low rate at which the turned-on area spreads and a high instantaneous power loss of conventional high voltage devices result in a reduced of di/dt capability for conventional thyristor devices.
With the prior art device, the main current that flows to the auxiliary thyristor region 15 is distributed to the main thyristor periphery 18 that faces toward the gate electrode 11 (i.e., distributed to the region just outside the main thyristor region 16 that is most proximal to the gate electrode). In general, the periphery length of the auxiliary gate facing the main thyristor region 16 is longer than the emitter periphery length of the auxiliary thyristor region 15. As a result, the main current flows only to the gate periphery 17 during the initial turned-on stage, and then must flow through the auxiliary thyristor region 15 to be distributed to the main thyristor periphery 18. As noted above, the period of time for this to occur increases as the blocking voltage increases. In other words, the rate at which the turn-on area spreads to the main thyristor periphery 18 decreases as the blocking voltage of increases. The spread of the turned-on area, and thus the gate current, is slow enough to cause a build-up of electrical power at the auxiliary thyristor region 15, leading to a concentration of power consumption at the initial turn on-area of the auxiliary thyristor region 15 during the initial turn-on stage. This can be a particularly troublesome problem with high voltages (i.e., use of high voltage thyristors).
Increasing the gate current (“IG”) may improve the di/dt capability, but only by a marginal amount. For example, if an IG that is three to five times greater than the minimum threshold current (“IGT”) is used to achieve the turn-on mode for the device, the initial turned-on area may be increased. Yet, the initial turned-on area still remains at or near the gate periphery 18. Thus, despite the application of high IG, the di/dt capability of, for example, a conventional 6.5 kV thyristor still hovers around 100 A/μs, whereas a di/dt capability of greater than 100 A/μs is required for most practical applications. One reason for this marginal improvement in di/dt capability is the failure to sufficiently reduce power consumption at the auxiliary thyristor region 15. One way to reduce power consumption is to facilitate the spread of the initial turned-on area to the main thyristor periphery 18 at a faster rate. However, as explained above, the initial turned-on area with the prior art thyristor cannot spread to the main thyristor periphery 18 quick enough.
Other prior art thyristor configurations include placing a high density of short dots 5 at the main thyristor periphery 18. As can be seen by FIGS. 1C-1D, the auxiliary thyristor region 15 has a limited area, and each short dot 5 of the main thyristor periphery 18 serves as a path that can bypass displacement current created by dv/dt at the pB-nB junction 19 of the auxiliary thyristor gate area. In situations where the short dot 5 density at the main thyristor periphery 18 is the same as the short dot 5 density the main thyristor region 16, the displacement current that flows through the short dots 5 becomes greater than the current flowing through the short dots 5 in main thyristor region 16. As the result, the dv/dt capability decreases. A higher shot dot 5 density at the main thyristor periphery 18, however, can be applied to increase the dv/dt capability by reducing the voltage drop caused by the displacement current flowing through the region underneath of the main thyristor periphery 18 (or main emitter periphery) to each short dot 5.
However, the high density short dot 5 layout at the main thyristor periphery 18 also increases the current required to make the entire main periphery 18 of the thyristor turn-on all at once. This results in an increased amount of time required for the main current flow to shift from the auxiliary thyristor region 15 to the main thyristor periphery 18, which again results in a decreased di/dt capability. While the introduction of a higher short dot 5 density layout may to improve dv/dt capability, the di/dt capability does not improve, and may even decrease. Thus, with such a higher short dot 5 density scheme, the di/dt capability still hovers around 100 A/μs for a conventional 6.5 kV thyristor, which is too low for most practical applications.
Further prior art thyristor configurations include a hybrid thyristor structure having an auxiliary thyristor gate, an interdigitated gate structure, and a grooved structure between the gate periphery and the main thyristor periphery 18. Without the grooved structure, the auxiliary thyristor region 15 is turned on by input of external gate current so that the turn-on current flows from the auxiliary thyristor region 15 to a periphery of the nE layer 4 (i.e., nE layer periphery) by way of an interdigitated gate electrode 11 and the nE layer periphery. When the voltage drop between the interdigitated gate electrode 11 and the nE layer 4 exceeds a threshold voltage for the pB-nE junction 19, the main thyristor periphery 18 initiates a turned-on mode. As noted above, the spread of the turned-on area between the gate periphery 17 to the main thyristor periphery 18 is decreased as the blocking voltage increases, and initial turn-on loss consumption concentrates at the gate periphery 17. To improve the initial turn-on loss consumption at the gate periphery 17, an auxiliary thyristor arrangement with a grooved structure between the gate periphery 17 and the main thyristor periphery 18 can be used. The grooved structure is effective to reduce the initial turn-on area along with the main thyristor periphery 18. Yet, even with this grooved structure, the increase in the di/dt capability is marginal, still hovering around 100 A/μs for a 6.5 kV class thyristor. This is because the main thyristor periphery 18 has a certain length, thus the initial turn-on current still concentrates to the periphery of the auxiliary thyristor until the main thyristor periphery turns on. Therefore, the groove structure does not have high di/dt capability, especially for high voltage thyristor applications. Further, the grooved structure has a weak point regarding dv/dt capability because of displacement current of the auxiliary thyristor and flows to the rest of the groove area. As a result, by adoption of the groove, dv/dt capability decreases.
In addition to the disadvantages described above, use of the conventional thyristor of FIG. 1A can be problematic when used in conjunction with snubber circuits and, in particular, resistance-capacitance snubber (“RC snubber” or “CR snubber”) circuits. If a conventional thyristor in connection with a CR snubber circuit is turn-on by IG, the snubber circuit first discharges current flow to the thyristor, after which the main circuit current flows to the thyristor. In such a situation, the auxiliary thyristor region 15 must be kept turned-on until the main current arrives at a threshold level to maintain a longer turned-on time at the main thyristor periphery 18. If the auxiliary thyristor region 15 is not kept on, then the auxiliary thyristor region 15 will have already transitioned to an off state due to a low main current flow. The off state will prevent spreading of the turn-on area to the main thyristor region 16, which may even lead to di/dt failure by the main current flow. In order to prevent the failure mode with such a configuration, an application of multiple gate input signals may be used, as opposed to one a gate input pulse used to initiate the turned-on mode. In addition, a special structure exhibiting different holding currents at the auxiliary thyristor region 15 and the main thyristor region 16 can be used. Yet, these require a more complex gate circuit design, increasing cost and complexity. It is therefore desired to generate a thyristor device exhibiting improved di/dt capability without relying on an auxiliary thyristor gate structure.
Another problem associated with the low di/dt characteristic exhibited by the prior art is that lower di/dt capabilities generally cause an increase in temperature at the initial turned-on area. Other factors may include applied voltage (“V”) to the thyristor, current flow (i) applied to the thyristor, the volume of the initial turned-on area (“A”), and specific heat of the material comprising the thyristor. Nonetheless, the increase in temperature can cause further consumption power, and a low di/dt contributes to the increase in temperature. In addition, the avalanche voltage of conventional thyristors is also temperature dependent. For instance, with a conventional 6.5 kV thyristor, the avalanche voltage drastically decreases when the junction temperature exceeds 150 degrees Celsius. This demonstrated temperature dependency is more pronounced as the voltage applied is increased (i.e., with higher blocking voltage). Moreover, with conventional thyristors, the thyristor device tends to break over due to an increase of leakage current at the high junction temperature.
As noted above, the blocking voltage exhibits a temperature dependency. For example, within a certain temperature range, the blocking voltage can increase approximately 10%/100 C. FIG. 1E shows schematic blocking voltage tendencies associated with different voltage thyristor products (e.g., a 6500V product, a 4500V product, and a 2500V product). In the case of a 6500V product, the blocking voltage at 25 C decreases as temperature decreases, and increases as temperature increases. This is seen in FIG. 1E by the blocking voltage decreasing to 6000V at negative 100 C.° and increases to 6800V at positive 200 C°. But, as the temperature increases from around 200 C.°, the blocking voltage gradually decreases.
The tendency of the change in blocking voltage can depend on the impurity density of the n-base layer. As the impurity density decreases, the tendency becomes conspicuous and maximum voltage occurs at a lower temperature, as compared to highly doped impurity products. An increase in temperature for lower voltage products (e.g., 4500V and 2500V products) also increases the blocking voltage, but at a lower rate as compared to the 6500V product. Further, with the lower voltage products, the temperature at which the blocking voltage begins to decrease with a rise in temperature is a higher temperature, as compared to the higher voltage products. One reason for this can be due to the difference of collision probability of electrons and holes to silicon lattices. As a result, high blocking voltage products that have lower doped impurities can have a wider depletion layer width than low blocking voltage products. This may be one reason for the temperature dependency difference between high voltage and low voltage products. By a combination of the above temperature dependency of blocking voltage and increase of temperature rise of initial turn-on area as blocking voltage increases, the di/dt capability decreases as blocking voltage increases.
The present invention is directed toward overcoming one or more of the above-identified problems.